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| ? 2005-2016 microchip technology inc. ds20001952c-page 1 mcp23017/mcp23s17 features 16-bit remote bidirectional i/o port: - i/o pins default to input high-speed i 2 c interface ( mcp23017 ): -100khz -400khz -1.7mhz high-speed spi interface ( mcp23s17 ): - 10 mhz (maximum) three hardware address pins to allow up to eight devices on the bus configurable interrupt output pins: - configurable as active-high, active-low or open-drain inta and intb can be configured to operate independently or together configurable interrupt source: - interrupt-on-change from configured register defaults or pin changes polarity inversion register to configure the polarity of the input port data external reset input low standby current: 1 a (max.) operating voltage: - 1.8v to 5.5v @ -40c to +85c - 2.7v to 5.5v @ -40c to +85c - 4.5v to 5.5v @ -40c to +125c packages 28-pin qfn, 6 x 6 mm body 28-pin soic, wide, 7.50 mm body 28-pin spdip, 300 mil body 28-pin ssop, 5.30 mm body package types 23 4 5 6 1 7 v ss nc 15 16 17 18 19 20 21 gpa4 gpa3 gpa2 gpa1 gpa0 v dd intb sck sda nc a0a1 a2 reset 23 24 25 26 27 28 22 gpb3 gpb2 gpb1 gpb0 gpa7 gpa6 gpa5 10 11 8 9 121314 gpb5 gpb6 gpb7 gpb4 inta gpb0 gpb1 gpb2 gpb3 inta gpb4 nc nc gpb5 gpb6 gpb7 sck gpa7 gpa6 gpa5 gpa4 gpa3 gpa2 gpa1 gpa0 v dd v ss a2a1 a0 sda 12 3 4 5 6 7 8 9 10 11 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 intb reset ep29 * spdip ssop soic qfn * includes exposed thermal pad; see ta b l e 2 - 1 . 23 4 5 6 1 7 v ss cs 15 16 17 18 19 20 21 gpa4 gpa3 gpa2 gpa1 gpa0 v dd intb si so a0a1 a2 reset 23 24 25 26 27 28 22 gpb3 gpb2 gpb1 gpb0 gpa7 gpa6 gpa5 10 11 8 9 121314 gpb5 gpb6 gpb7 gpb4 inta sck ep 29 * gpb0 gpb1 gpb2 gpb3 inta gpb4 so cs gpb5 gpb6 gpb7 sck gpa7 gpa6 gpa5 gpa4 gpa3 gpa2 gpa1 gpa0 v dd v ss a2a1 a0 si 12 3 4 5 6 7 8 9 10 11 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 intb reset mcp23s17 mcp23017 16-bit i/o expander wi th serial interface downloaded from: http:///
mcp23017/mcp23s17 ds20001952c-page 2 ? 2005-2016 microchip technology inc. functional block diagram gpb7gpb6 gpb5 gpb4 gpb3 gpb2 gpb1 gpb0 i 2 c control gpio scl sda reset inta 16 configuration/ 8 a2:a0 3 control registers spi si so sck cs mcp23s17 mcp23017 gpa7 gpa6 gpa5 gpa4 gpa3 gpa2 gpa1 gpa0 intb interrupt gpio serializer/ deserializer logic decode downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 3 mcp23017/mcp23s17 1.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ ...................-65c to +150c voltage on v dd with respect to v ss .......................................................................................................... -0.3v to +5.5v voltage on all other pins with respect to v ss (except v dd )............................................................. -0.6v to (v dd + 0.6v) total power dissipation........................................................................................................ .................................700 mw maximum current out of v ss pin ........................................................................................................................... 150 ma maximum current into v dd pin ..............................................................................................................................125 ma input clamp current, i ik (v i < 0 or v i > v dd ).......................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd )...................................................................................................20 ma maximum output current sunk by any output pin .................................................................................. ..................25 ma maximum output current sourced by any output pin ............................................................................... ................25 ma esd protection on all pins (hbm:mm) ............................................................................................ ..................4 kv:400v ? notice : stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indi cated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended period s may affect device reliability. downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 4 ? 2005-2016 microchip technology inc. 1.1 dc characteristics table 1-1: dc characteristics electrical specifications: unless otherwise noted, 1.8v ?? v dd ? 5.5v at -40 ? c ? t a ? +125 ? c param. no. characteristic sym. min. typ. ( 1 ) max. units conditions d001 supply voltage v dd 1.8 5.5 v d002 v dd start voltage to ensure power-on reset v por v ss v d003 v dd rise rate to ensure power-on reset sv dd 0.05 v/ms design guidance only. not tested. d004 supply current i dd 1 ma scl/sck = 1 mhz d005 standby current i dds8 1 a - 4 0 c ? t a ? +85c 3 a 4 . 5 v ?? v dd ?? 5.5v +85c ? t a ? +125 ? c ( note 1 ) input low voltage d030 a0, a1, a2 (ttl buffer) v il v ss 0 . 1 5v dd v d031 cs , gpio, scl/sck, sda, reset (schmitt trigger) v il v ss 0 . 2 v dd v input high voltage d040 a0, a1, a2 (ttl buffer) v ih 0.25 v dd + 0.8 v dd v d041 cs , gpio, scl/sck, sda, reset (schmitt trigger) v ih 0.8 v dd v dd v for entire v dd range input leakage current d060 i/o port pins i il 1 a v ss ?? v pin ?? v dd output leakage current d065 i/o port pins i lo 1 a v ss ?? v pin ?? v dd d070 gpio weak pull-up current i pu 40 75 115 a v dd = 5v gp pins = v ss output low-voltage d080 gpio v ol 0 . 6v i ol = 8.0 ma v dd = 4.5v int v ol 0 . 6v i ol = 1.6 ma v dd = 4.5v so, sda v ol 0 . 6v i ol = 3.0 ma v dd = 1.8v sda v ol 0 . 8v i ol = 3.0 ma v dd = 4.5v output high-voltage d090 gpio, int, so v oh v dd C 0.7 v i oh = -3.0 ma v dd = 4.5v v dd C 0.7 i oh = -400 a v dd = 1.8v capacitive loading specs on output pins d101 gpio, so, int c io 5 0p f d102 sda c b 400 pf note 1: this parameter is characterized, not 100% tested. downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 5 mcp23017/mcp23s17 1.2 ac characteristics figure 1-1: load conditions fo r device timing specifications figure 1-2: reset and device reset timer timing table 1-2: device reset specifications ac characteristics: unless otherwise noted, 1.8v ?? v dd ? 5.5v at -40 ? c ? t a ? +125 ? c param. no. characteristic sym. min. typ. ( 1 ) max. units conditions 30 reset pulse width (low) t rstl 1 s 32 device active after reset high t hld 0n sv dd = 5.0v 34 output high-impedance from reset low t ioz 1 s note 1: this parameter is characterized, not 100% tested. 135 pf 1k ? v dd scl and sda pin mcp23017 50 pf pin v dd reset internal reset 34 output pin 32 30 downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 6 ? 2005-2016 microchip technology inc. figure 1-3: i 2 c bus start/stop bits timing figure 1-4: i 2 c bus data timing table 1-3: i 2 c bus data requirements i 2 c interface ac characteristics: unless otherwise noted, 1.8v ?? v dd ? 5.5v at -40 ? c ? t a ? +125 ? c , r pu (scl, sda) = 1 k ? , c l (scl, sda) = 135 pf param. no. characteristic sym. min. typ. max. units conditions 100 clock high time: t high 100 khz mode 4.0 s 1.8v C 5.5v 400 khz mode 0.6 s 2.7v C 5.5v 1.7 mhz mode 0.12 s 4.5v C 5.5v 101 clock low time: t low 100 khz mode 4.7 s 1.8v C 5.5v 400 khz mode 1.3 s 2.7v C 5.5v 1.7 mhz mode 0.32 s 4.5v C 5.5v 102 sda and scl rise time: t r ( 1 ) 100 khz mode 1000 ns 1.8v C 5.5v 400 khz mode 20 + 0.1 c b ( 2 ) 300 ns 2.7v C 5.5v 1.7 mhz mode 20 160 ns 4.5v C 5.5v 103 sda and scl fall time: t f ( 1 ) 100 khz mode 300 ns 1.8v C 5.5v 400 khz mode 20 + 0.1 c b ( 2 ) 300 ns 2.7v C 5.5v 1.7 mhz mode 20 80 ns 4.5v C 5.5v note 1: this parameter is characterized, not 100% tested. 2: c b is specified to be from 10 to 400 pf. 91 93 scl sda start condition stop condition 90 92 90 91 92 100 101 103 106 107 109 109 110 102 scl sdain sda out downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 7 mcp23017/mcp23s17 90 start condition setup time: t su:sta 100 khz mode 4.7 s 1.8v C 5.5v 400 khz mode 0.6 s 2.7v C 5.5v 1.7 mhz mode 0.16 s 4.5v C 5.5v 91 start condition hold time: t hd:sta 100 khz mode 4.0 s 1.8v C 5.5v 400 khz mode 0.6 s 2.7v C 5.5v 1.7 mhz mode 0.16 s 4.5v C 5.5v 106 data input hold time: t hd:dat 100 khz mode 0 3.45 s 1.8v C 5.5v 400 khz mode 0 0.9 s 2.7v C 5.5v 1.7 mhz mode 0 0.15 s 4.5v C 5.5v 107 data input setup time: t su:dat 100 khz mode 250 ns 1.8v C 5.5v 400 khz mode 100 ns 2.7v C 5.5v 1.7 mhz mode 0.01 s 4.5v C 5.5v 92 stop condition setup time: t su:sto 100 khz mode 4.0 s 1.8v C 5.5v 400 khz mode 0.6 s 2.7v C 5.5v 1.7 mhz mode 0.16 s 4.5vC5.5v 109 output valid from clock: t aa 100 khz mode 3.45 s 1.8v C 5.5v 400 khz mode 0.9 s 2.7v C 5.5v 1.7 mhz mode 0.18 s 4.5v C 5.5v 110 bus free time: t buf 100 khz mode 4.7 s 1.8v C 5.5v 400 khz mode 1.3 s 2.7v C 5.5v 1.7 mhz mode n/a n/a s 4.5v C 5.5v 111 bus capacitive loading: c b 100 khz and 400 khz 400 pf note 1 1.7 mhz 100 pf note 1 112 input filter spike suppression (sda and scl): t sp 100 khz and 400 khz 50 ns 1.7 mhz 10 ns spike suppression off table 1-3: i 2 c bus data requirements (continued) i 2 c interface ac characteristics: unless otherwise noted, 1.8v ?? v dd ? 5.5v at -40 ? c ? t a ? +125 ? c , r pu (scl, sda) = 1 k ? , c l (scl, sda) = 135 pf param. no. characteristic sym. min. typ. max. units conditions note 1: this parameter is characterized, not 100% tested. 2: c b is specified to be from 10 to 400 pf. downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 8 ? 2005-2016 microchip technology inc. figure 1-5: spi input timing figure 1-6: spi output timing table 1-4: spi interface requirements spi interface ac characteristics: unless otherwise noted, 1.8v ?? v dd ? 5.5v at -40 ? c ? t a ? +125 ? c param. no. characteristic sym. min. typ. max. units conditions clock frequency f clk 5 mhz 1.8v C 5.5v 10 mhz 2.7v C 5.5v 10 mhz 4.5v C 5.5v 1c s setup time t css 50 ns 2c s hold time t csh 100 ns 1.8v C 5.5v 50 ns 2.7v C 5.5v 3c s disable time t csd 100 ns 1.8v C 5.5v 50 ns 2.7v C 5.5v 4 data setup time t su 20 ns 1.8v C 5.5v 10 ns 2.7v C 5.5v note 1: this parameter is characterized, not 100% tested. sck si so 1 5 4 7 6 3 10 2 lsb in msb in high-impedance 11 mode 1,1 mode 0,0 note 1: when using spi mode 1,1 the cs pin needs to be toggled once before the first communication after power-up. cs ( 1 ) cs sck so 8 13 msb out lsb out 2 14 dont care si mode 1,1 mode 0,0 9 12 downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 9 mcp23017/mcp23s17 figure 1-7: gpio and int timing 5d a t a h o l d t i m e t hd 20 ns 1.8v C 5.5v 10 ns 2.7v C 5.5v 6c l k r i s e t i m e t r 2 s note 1 7c l k f a l l t i m e t f 2 s note 1 8c l o c k h i g h t i m e t hi 90 ns 1.8v C 5.5v 45 ns 2.7v C 5.5v 9 clock low time t lo 90 ns 1.8v C 5.5v 45 ns 2.7v C 5.5v 10 clock delay time t cld 50 ns 11 clock enable time t cle 50 ns 12 output valid from clock low t v 90 ns 1.8v C 5.5v 45 ns 2.7v C 5.5v 13 output hold time t ho 0n s 14 output disable time t dis 100 ns table 1-4: spi interface requirements (continued) spi interface ac characteristics: unless otherwise noted, 1.8v ?? v dd ? 5.5v at -40 ? c ? t a ? +125 ? c param. no. characteristic sym. min. typ. max. units conditions note 1: this parameter is characterized, not 100% tested. 50 scl/sck sda/si in gpn pin d0 d1 lsb of data byte zero during a write or read int pin int pin active 51 command, depending on parameter output gpn pin input inactive 53 52 register loaded downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 10 ? 2005-2016 microchip technology inc. table 1-5: gp and int pins requirements gp and int pins ac characteristics: unless otherwise noted, 1.8v ?? v dd ? 5.5v at -40 ? c ? t a ? +125 ? c param. no. characteristic sym. min. typ. max. units conditions 50 serial data to output valid t gpov 5 0 0n s 51 interrupt pin disable time t intd 6 0 0n s 52 gp input change to register valid t gpiv 4 5 0n s 53 ioc event to int active t gpint 6 0 0n s glitch filter on gp pins t glitch 1 5 0n s note 1 note 1: this parameter is characterized, not 100% tested. downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 11 mcp23017/mcp23s17 2.0 pin descriptions the descriptions of the pins are listed in tab l e 2 - 1 . table 2-1: pinout description pin name qfn soic spdip ssop pin type function gpb0 25 1 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpb1 26 2 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpb2 27 3 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpb3 28 4 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpb4 1 5 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpb5 2 6 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpb6 3 7 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpb7 4 8 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. v dd 5 9 p power v ss 6 10 p ground nc/cs 7 11 i nc ( mcp23017 )/chip select ( mcp23s17 ) sck 8 12 i serial clock input sda/si 9 13 i/o serial data i/o ( mcp23017 )/serial data input ( mcp23s17 ) nc/so 10 14 o nc ( mcp23017 )/serial data out ( mcp23s17 ) a0 11 15 i hardware address pin. must be externally biased. a1 12 16 i hardware address pin. must be externally biased. a2 13 17 i hardware address pin. must be externally biased. reset 14 18 i hardware reset. must be externally biased. intb 15 19 o interrupt output for portb. can be configured as active-high, active-low or open-drain. inta 16 20 o interrupt output for porta. can be configured as active-high, active-low or open-drain. gpa0 17 21 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpa1 18 22 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpa2 19 23 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpa3 20 24 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpa4 21 25 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpa5 22 26 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpa6 23 27 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. gpa7 24 28 i/o bidirectional i/o pin. can be enabled for inte rrupt-on-change and/or internal weak pull-up resistor. ep 29 exposed thermal pad. either connect to v ss , or leave unconnected. downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 12 ? 2005-2016 microchip technology inc. 3.0 device overview the mcp23017/mcp23s17 (mcp23x17) device family provides 16-bit, general purpose parallel i/o expansion for i 2 c bus or spi applications. the two devices differ only in the serial interface: mcp23017 C i 2 c interface mcp23s17 C spi interface the mcp23x17 consists of multiple 8-bit configuration registers for input, output and polarity selection. the system master can enable the i/os as either inputs or outputs by writing the i/o configuration bits (iodira/b). the data for each input or output is kept in the corresponding input or output register. the polarity of the input port register can be inverted with the polarity inversion register. all registers can be read by the system master. the 16-bit i/o port functionally consists of two 8-bit ports (porta and portb). the mcp23x17 can be configured to operate in the 8-bit or 16-bit modes via iocon.bank. there are two interrupt pins, inta and intb, that can be associated with their respective ports, or can be logically ored together so that both pins will activate if either port causes an interrupt. the interrupt output can be configured to activate under two conditions (mutually exclusive): 1. when any input state differs from its corresponding input port register state. this is used to indicate to the system master that an input state has changed. 2. when an input state differs from a preconfigured register value (defval register). the interrupt capture register captures port values at the time of the interrupt, thereby saving the condition that caused the interrupt. the power-on reset (por) sets the registers to their default values and initializes the device state machine. the hardware address pins are used to determine the device address. 3.1 power-on reset (por) the on-chip por circuit holds the device in reset until v dd has reached a high enough voltage to deactivate the por circuit (i.e., release the device from reset). the maximum v dd rise time is specified in section 1.0 ?electrical characteristics? . when the device exits the por condition (releases reset), device operating parameters (i.e., voltage, temperature, serial bus frequency, etc.) must be met to ensure proper operation. 3.2 serial interface this block handles the functionality of the i 2 c ( mcp23017 ) or spi ( mcp23s17 ) interface protocol. the mcp23x17 contains 22 individual registers (11 register pairs) that can be addressed through the serial interface block, as shown in table 3-1 . table 3-1: register addresses address iocon.bank = 1 address iocon.bank = 0 access to: 00h 00h iodira 10h 01h iodirb 01h 02h ipola 11h 03h ipolb 02h 04h gpintena 12h 05h gpintenb 03h 06h defvala 13h 07h defvalb 04h 08h intcona 14h 09h intconb 05h 0ah iocon 15h 0bh iocon 06h 0ch gppua 16h 0dh gppub 07h 0eh intfa 17h 0fh intfb 08h 10h intcapa 18h 11h intcapb 09h 12h gpioa 19h 13h gpiob 0ah 14h olata 1ah 15h olatb downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 13 mcp23017/mcp23s17 3.2.1 byte mode and sequential mode the mcp23x17 family has the ability to operate in byte mode or sequential mode (iocon.seqop). byte mode disables automatic address pointer incrementing. when operating in byte mode, the mcp23x17 family does not increment its internal address counter after each byte during the data transfer. this gives the ability to continually access the same address by providing extra clocks (without additional control bytes). this is useful for polling the gpio register for data changes or for continually writing to the output latches. a special mode (byte mode with iocon.bank = 0 ) causes the address pointer to toggle between associated a/b register pairs. for example, if the bank bit is cleared and the address pointer is initially set to address 12h (gpioa) or 13h (gpiob), the pointer will toggle between gpioa and gpiob. note that the address pointer can initially point to either address in the register pair. sequential mode enables automatic address pointer incrementing. when operating in sequential mode, the mcp23x17 family increments its address counter after each byte during the data transfer. the address pointer automatically rolls over to address 00h after accessing the last register. these two modes are not to be confused with single writes/reads and continuous writes/reads that are serial protocol sequences. for example, the device may be configured for byte mode and the master may perform a continuous read. in this case, the mcp23x17 would not increment the address pointer and would repeatedly drive data from the same location. 3.2.2 i 2 c interface 3.2.2.1 i 2 c write operation the i 2 c write operation includes the control byte and register address sequence, as shown in figure 3-1 . this sequence is followed by eight bits of data from the master and an acknowledge (ack) from the mcp23017. the operation is ended with a stop (p) or restart (sr) condition being generated by the master. data is written to the mcp23017 after every byte transfer. if a stop or restart condition is generated during a data transfer, the data will not be written to the mcp23017. both byte writes and sequential writes are supported by the mcp23017. if sequential mode is enabled (iocon, seqop = 0 ) (default), the mcp23017 increments its address counter after each ack during the data transfer. figure 3-1: byte and sequential write s p w op addr d in d in .... s w op addr d in p byte sequential s p sr w r op addr d in - start - restart - stop - write - read - device opcode - device register address - data out from mcp23017 - data in to mcp23017 d out downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 14 ? 2005-2016 microchip technology inc. 3.2.2.2 i 2 c read operation i 2 c read operations include the control byte sequence, as shown in figure 3-2 . this sequence is followed by another control byte (including the start condition and ack) with the r/w bit set (r/w = 1 ). the mcp23017 then transmits the data contained in the addressed register. the sequence is ended with the master generating a stop or restart condition. figure 3-2: byte and sequential read 3.2.2.3 i 2 c sequential write/read for sequential operations (write or read), instead of transmitting a stop or restart condition after the data transfer, the master clocks the next byte pointed to by the address pointer (see section 3.2.1 ?byte mode and sequential mode? for details regarding sequential operation control). the sequence ends with the master sending a stop or restart condition. the mcp23017 address pointer will roll over to address zero after reaching the last register address. refer to figure 3-3 . figure 3-3: mcp23017 i 2 c device protocol sr r op d out d out .... p s w op sr r op d out p byte sequential s w op s p sr w r op addr d in d in .... p w op addr d out d out .... p sr w op d in d in .... p p sr r d out d out .... p op .... p sr op d in .... p d in d out d out s r op downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 15 mcp23017/mcp23s17 3.2.3 spi interface 3.2.3.1 spi write operation the spi write operation is started by lowering cs . the write command (slave address with r/w bit cleared) is then clocked into the device. the opcode is followed by an address and at least one data byte. 3.2.3.2 spi read operation the spi read operation is started by lowering cs . the spi read command (slave address with r/w bit set) is then clocked into the device. the opcode is followed by an address, with at least one data byte being clocked out of the device. 3.2.3.3 spi sequential write/read for sequential operations, instead of deselecting the device by raising cs , the master clocks the next byte pointed to by the address pointer. (see section 3.2.1 ?byte mode and sequential mode? for details regarding sequential operation control). the sequence ends by the raising of cs . the mcp23s17 address pointer will roll over to address zero after reaching the last register address. 3.3 hardware address decoder the hardware address pins are used to determine the device address. to address a device, the correspond- ing address bits in the control byte must match the pin state. the pins must be biased externally. 3.3.1 addressing i 2 c devices ( mcp23017 ) the mcp23017 is a slave i 2 c interface device that supports 7-bit slave addressing, with the read/write bit filling out the control byte. the slave address contains four fixed bits and three user-defined hardware address bits (pins a2, a1 and a0). figure 3-4 shows the control byte format. 3.3.2 addressing spi devices ( mcp23s17 ) the mcp23s17 is a slave spi device. the slave address contains four fixed bits and three user-defined hardware address bits (if enabled via iocon.haen) (pins a2, a1 and a0) with the read/write bit filling out the control byte. figure 3-5 shows the control byte format. the address pins should be externally biased even if disabled (iocon.haen = 0 ). figure 3-4: i 2 c control byte format figure 3-5: spi control byte format figure 3-6: i 2 c addressing registers s 0 1 0 0 a2a1a0r/w ack start bit slave address r/w bit ack bit control byte r/w = 0 = write r/w = 1 = read 0 1 0 0 a2 a1 a0 r/w slave address r/w bit control byte r/w = 0 = write r/w = 1 = read cs s0100a2a1a00 ack * a7 a6 a5 a4 a3 a2 a1 a0 ack * device opcode register address r/w = 0 *the acks are provided by the mcp23017. downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 16 ? 2005-2016 microchip technology inc. figure 3-7: spi addressing registers 3.4 gpio port the gpio module is a general purpose, 16-bit wide, bidirectional port that is functionally split into two 8-bit wide ports. the gpio module contains the data ports (gpion), internal pull-up resistors and the output latches (olatn). reading the gpion register reads the value on the port. reading the olatn register only reads the latches, not the actual value on the port. writing to the gpion register actually causes a write to the latches (olatn). writing to the olatn register forces the associated output drivers to drive to the level in olatn. pins configured as inputs turn off the associated output driver and put it in high-impedance. 0100a2 * a1 * a0 * r/w a7 a6 a5 a4 a3 a2 a1 a0 device opcode register address cs * address pins are enabled/disabled via iocon.haen. table 3-2: summary of registers associ ated with the gpio ports (bank = 1 ) register name address (hex) b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 por/rst value iodira 00 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 i p o l a 0 1i p 7i p 6i p 5i p 4i p 3i p 2i p 1i p 0 0000 0000 gpintena 02 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 gppua 06 pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 gpioa 09 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olata 0a ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 iodirb 10 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 ipolb 11 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 gpintenb 12 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 gppub 16 pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 gpiob 19 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olatb 1a ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 table 3-3: summary of registers associ ated with the gpio ports (bank = 0 ) register name address (hex) b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 por/rst value iodira 00 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 iodirb 01 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 i p o l a 0 2i p 7i p 6i p 5i p 4i p 3i p 2i p 1i p 0 0000 0000 ipolb 03 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 gpintena 04 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 gpintenb 05 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 gppua 0c pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 gppub 0d pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 gpioa 12 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 gpiob 13 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olata 14 ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 olatb 15 ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 17 mcp23017/mcp23s17 3.5 configuration and control registers there are 21 registers associated with the mcp23x17, as shown in tables 3-4 and 3-5 . the two tables show the register mapping with the two bank bit values. ten registers are associated with porta and ten are associated with portb. one register (iocon) is shared between the two ports. the porta registers are identical to the portb registers, therefore, they will be referred to without differentiating between the port designation (i.e., they will not have the a or b designator assigned) in the register tables. table 3-4: control register summary (iocon.bank = 1 ) register name address (hex) b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 por/rst value iodira 00 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 i p o l a 0 1i p 7i p 6i p 5i p 4i p 3i p 2i p 1i p 0 0000 0000 gpintena 02 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 d e f v a l a 0 3 d e f 7d e f 6d e f 5d e f 4d e f 3d e f 2d e f 1d e f 0 0000 0000 intcona 04 ioc7 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 0000 0000 iocon 05 bank mirror seqop disslw haen odr intpol 0000 0000 gppua 06 pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 intfa 07 int7 int6 int5 int4 int3 int2 int1 into 0000 0000 intcapa 08 icp7 icp6 icp5 icp4 icp3 icp2 icp1 icp0 0000 0000 gpioa 09 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olata 0a ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 iodirb 10 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 ipolb 11 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 gpintenb 12 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 defvalb 13 def7 def6 def5 def4 def3 def2 def1 def0 0000 0000 intconb 14 ioc7 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 0000 0000 iocon 15 bank mirror seqop disslw haen odr intpol 0000 0000 gppub 16 pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 intfb 17 int7 int6 int5 int4 int3 int2 int1 into 0000 0000 intcapb 18 icp7 icp6 icp5 icp4 icp3 icp2 icp1 icp0 0000 0000 gpiob 19 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olatb 1a ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 table 3-5: control register summary (iocon.bank = 0 ) register name address (hex) b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 por/rst value iodira 00 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 iodirb 01 io7 io6 io5 io4 io3 io2 io1 io0 1111 1111 i p o l a 0 2i p 7i p 6i p 5i p 4i p 3i p 2i p 1i p 0 0000 0000 ipolb 03 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 0000 0000 gpintena 04 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 gpintenb 05 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 0000 0000 d e f v a l a 0 6 d e f 7d e f 6d e f 5d e f 4d e f 3d e f 2d e f 1d e f 0 0000 0000 defvalb 07 def7 def6 def5 def4 def3 def2 def1 def0 0000 0000 intcona 08 ioc7 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 0000 0000 intconb 09 ioc7 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 0000 0000 iocon 0a bank mirror seqop disslw haen odr intpol 0000 0000 iocon 0b bank mirror seqop disslw haen odr intpol 0000 0000 gppua 0c pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 gppub 0d pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 0000 0000 downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 18 ? 2005-2016 microchip technology inc. 3.5.1 i/o direction register controls the direction of the data i/o. when a bit is set, the corresponding pin becomes an input. when a bit is clear, the corresponding pin becomes an output. 3.5.2 input polarity register this register allows the user to configure the polarity on the corresponding gpio port bits. if a bit is set, the corresponding gpio register bit will reflect the inverted value on the pin. intfa 0e int7 int6 int5 int4 int3 int2 int1 into 0000 0000 intfb 0f int7 int6 int5 int4 int3 int2 int1 into 0000 0000 intcapa 10 icp7 icp6 icp5 icp4 icp3 icp2 icp1 icp0 0000 0000 intcapb 11 icp7 icp6 icp5 icp4 icp3 icp2 icp1 icp0 0000 0000 gpioa 12 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 gpiob 13 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0000 0000 olata 14 ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 olatb 15 ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 0000 0000 table 3-5: control register summary (iocon.bank = 0 ) (continued) register name address (hex) b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 por/rst value register 3-1: iodir: i/o di rection register (addr 0x00) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 io7 io6 io5 io4 io3 io2 io1 io0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 io<7:0>: controls the direction of data i/o <7:0> 1 = pin is configured as an input. 0 = pin is configured as an output. register 3-2: ipol: input polarity port register (addr 0x01) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 ip<7:0>: controls the polarity inversion of the input pins <7:0> 1 = gpio register bit reflects the opposite logic state of the input pin. 0 = gpio register bit reflects the same logic state of the input pin. downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 19 mcp23017/mcp23s17 3.5.3 interrupt-on-change control register the gpinten register controls the interrupt-on-change feature for each pin. if a bit is set, the corresponding pin is enabled for interrupt-on-change. the defval and intcon registers must also be configured if any pins are enabled for interrupt-on-change. 3.5.4 default compare register for interrupt-on-change the default comparison value is configured in the defval register. if enabled (via gpinten and intcon) to compare against the defval register, an opposite value on the associated pin will cause an interrupt to occur. register 3-3: gpinten: interrupt-on-change pins (addr 0x02) ( note 1 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gpint7 gpint6 gpint5 gpint4 gpint3 gpint2 gpint1 gpint0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 gpint<7:0>: general purpose i/o interrupt-on-change bits <7:0> 1 = enables gpio input pin for interrupt-on-change event. 0 = disables gpio input pin for interrupt-on-change event. note 1: refer to intcon. register 3-4: defval: default value register (addr 0x03) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 def7 def6 def5 def4 def3 def2 def1 def0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 def<7:0>: sets the compare value for pins configured for interrupt-on-chang e from defaults <7:0> ( note 1 ) if the associated pin level is the opposite from the register bit, an interrupt occurs. ( note 2 ) note 1: refer to intcon. 2: refer to intcon and gpinten. downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 20 ? 2005-2016 microchip technology inc. 3.5.5 interrupt control register the intcon register controls how the associated pin value is compared for the interrupt-on-change feature. if a bit is set, the corresponding i/o pin is compared against the associated bit in the defval register. if a bit value is clear, the corresponding i/o pin is compared against the previous value. 3.5.6 configuration register the iocon register contains several bits for configuring the device: the bank bit changes how the registers are mapped (see tables 3-4 and 3-5 for more details). if bank = 1 , the registers associated with each port are segregated. registers associated with porta are mapped from address 00h - 0ah and registers associated with portb are mapped from 10h - 1ah. if bank = 0 , the a/b registers are paired. for example, iodira is mapped to address 00h and iodirb is mapped to the next address (address 01h). the mapping for all registers is from 00h -15h. it is important to take care when changing the bank bit as the address mapping changes after the byte is clocked into the device. the address pointer may point to an invalid location after the bit is modified. for example, if the device is configured to automatically increment its internal address pointer, the following scenario would occur: bank = 0 write 80h to address 0ah (iocon) to set the bank bit once the write completes, the internal address now points to 0bh which is an invalid address when the bank bit is set. for this reason, when changing the bank bit, it is advised to only perform byte writes to this register. the mirror bit controls how the inta and intb pins function with respect to each other. when mirror = 1 , the intn pins are functionally ored so that an interrupt on either port will cause both pins to activate. when mirror = 0 , the int pins are separated. interrupt conditions on a port will cause its respective int pin to activate. the sequential operation ( seqop ) controls the incrementing function of the address pointer. if the address pointer is disabled, the address pointer does not automatically increment after each byte is clocked during a serial transfer. this feature is useful when it is desired to continuously poll (read) or modify (write) a register. the slew rate ( disslw ) bit controls the slew rate function on the sda pin. if enabled, the sda slew rate will be controlled when driving from a high to low. the hardware address enable ( haen ) bit enables/disables hardware addressing on the mcp23s17 only. the address pins (a2, a1 and a0) must be externally biased, regardless of the haen bit value. if enabled (haen = 1 ), the devices hardware address matches the address pins. if disabled (haen = 0 ), the devices hardware address is a2 = a1 = a0 = 0 . register 3-5: intcon: interrupt-on- change control regi ster (addr 0x04) ( note 1 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ioc7 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 ioc<7:0>: controls how the associated pin value is compared for interrupt-on-change <7:0> 1 = pin value is compared against the associated bit in the defval register. 0 = pin value is compared against the previous pin value. note 1: refer to intcon and gpinten. downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 21 mcp23017/mcp23s17 the open-drain ( odr ) control bit enables/disables the int pin for open-drain configuration. setting this bit overrides the intpol bit. the interrupt polarity ( intpol ) sets the polarity of the int pin. this bit is functional only when the odr bit is cleared, configuring the int pin as active push-pull. register 3-6: iocon: i/o expander configuratio n register (addr 0x05) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 bank mirror seqop disslw haen odr intpol bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 bank: controls how the registers are addressed 1 = the registers associated with each port are separated into different banks. 0 = the registers are in the same bank (addresses are sequential). bit 6 mirror: int pins mirror bit 1 = the int pins are internally connected 0 = the int pins are not connected. inta is associated with porta and intb is associated with portb bit 5 seqop: sequential operation mode bit 1 = sequential operation disabled, address pointer does not increment. 0 = sequential operation enabled, address pointer increments. bit 4 disslw: slew rate control bit for sda output 1 = slew rate disabled 0 = slew rate enabled bit 3 haen: hardware address enable bit ( mcp23s17 only) ( note 1 ) 1 = enables the mcp23s17 address pins. 0 = disables the mcp23s17 address pins. bit 2 odr: configures the int pin as an open-drain output 1 = open-drain output (overrides the intpol bit.) 0 = active driver output (intpol bit sets the polarity.) bit 1 intpol: this bit sets the polarity of the int output pin 1 = active-high 0 =active-low bit 0 unimplemented: read as 0 note 1: address pins are always enabled on the mcp23017. downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 22 ? 2005-2016 microchip technology inc. 3.5.7 pull-up resistor configuration register the gppu register controls the pull-up resistors for the port pins. if a bit is set and the corresponding pin is configured as an input, the corresponding port pin is internally pulled up with a 100 k ? resistor. 3.5.8 interrupt flag register the intf register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the gpinten register. a set bit indicates that the associated pin caused the interrupt. this register is read-only. writes to this register will be ignored. register 3-7: gppu: gpio pull-up resistor register (addr 0x06) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 pu<7:0> controls the weak pull-up resistors on each pin (when configured as an input) 1 = pull-up enabled 0 = pull-up disabled register 3-8: intf: interrupt flag register (addr 0x07) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 int7 int6 int5 int4 int3 int2 int1 int0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 int<7:0>: reflects the interrupt condition on the port. it reflects the change only if interrupts are enabled per gpinten<7:0>. 1 = pin caused interrupt. 0 = interrupt not pending downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 23 mcp23017/mcp23s17 3.5.9 interrupt captured register the intcap register captures the gpio port value at the time the interrupt occurred. the register is read-only and is updated only when an interrupt occurs. the register remains unchanged until the interrupt is cleared via a read of intcap or gpio. 3.5.10 port register the gpio register reflects the value on the port. reading from this register reads the port. writing to this register modifies the output latch (olat) register. register 3-9: intcap: interrupt capture d value for port register (addr 0x08) r-x r-x r-x r-x r-x r-x r-x r-x icp7 icp6 icp5 icp4 icp3 icp2 icp1 icp0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 icp<7:0>: reflects the logic level on the port pins at the time of interrupt due to pin change <7:0> 1 = logic-high 0 = logic-low register 3-10: gpio: general purpos e i/o port register (addr 0x09) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 gp<7:0>: reflects the logic level on the pins <7:0> 1 = logic-high 0 = logic-low downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 24 ? 2005-2016 microchip technology inc. 3.5.11 output latch register (olat) the olat register provides access to the output latches. a read from this register results in a read of the olat and not the port itself. a write to this register modifies the output latches that modifies the pins configured as outputs. 3.6 interrupt logic if enabled, the mcp23x17 activates the intn interrupt output when one of the port pins changes state or when a pin does not match the preconfigured default. each pin is individually configurable as follows: enable/disable interrupt via gpinten can interrupt on either pin change or change from default as configured in defval both conditions are referred to as interrupt-on-change (ioc). the interrupt control module uses the following registers/bits: iocon.mirror C controls if the two interrupt pins mirror each other gpinten C interrupt enable register intcon C controls the source for the ioc defval C contains the register default for ioc operation 3.6.1 inta and intb there are two interrupt pins: inta and intb. by default, inta is associated with gpan pins (porta) and intb is associated with gpbn pins (portb). each port has an independent signal which is cleared if its associated gpio or intcap register is read. 3.6.1.1 mirroring the int pins additionally, the intn pins can be configured to mirror each other so that any interrupt will cause both pins to go active. this is controlled via iocon.mirror. if iocon.mirror = 0 , the internal signals are routed independently to the inta and intb pads. if iocon.mirror = 1 , the internal signals are ored together and routed to the intn pads. in this case, the interrupt will only be cleared if the associated gpio or intcap is read (see ta bl e 3 - 6 ). 3.6.2 ioc from pin change if enabled, the mcp23x17 generates an interrupt if a mismatch condition exists between the current port value and the previous port value. only ioc-enabled pins will be compared. refer to registers 3-3 and 3-5 . 3.6.3 ioc from register default if enabled, the mcp23x17 generates an interrupt if a mismatch occurs between the defval register and the port. only ioc enabled pins are compared. refer to registers 3-3 , 3-4 and 3-5 . register 3-11: olat: output latch register 0 (addr 0x0a) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-0 ol<7:0>: reflects the logic level on the output latch <7:0> 1 = logic-high 0 = logic-low table 3-6: interrupt operation (iocon.mirror = 1 ) interrupt condition read portn ( 1 ) interrupt result gpioa porta clear portb unchanged gpiob porta unchanged portb clear gpioa and gpiob porta unchanged portb unchanged both porta and portb clear note 1: portn = gpion or intcapn downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 25 mcp23017/mcp23s17 3.6.4 interrupt operation the intn interrupt output can be configured as active-low, active-high or open-drain via the iocon register. only those pins that are configured as an input (iodir register) with interrupt-on-change (ioc) enabled (iointen register) can cause an interrupt. pins defined as an output have no effect on the interrupt output pin. input change activity on a port input pin that is enabled for ioc generates an internal device interrupt and the device captures the value of the port and copies it into intcap. the interrupt remains active until the intcap or gpio register is read. writing to these registers does not affect the interrupt. the interrupt condition is cleared after the lsb of the data is clocked out during a read command of gpio or intcap. the first interrupt event causes the port contents to be copied into the intcap register. subsequent interrupt conditions on the port will not cause an interrupt to occur as long as the interrupt is not cleared by a read of intcap or gpio. 3.6.5 interrupt conditions there are two possible configurations that cause interrupts (configured via intcon): 1. pins configured for interrupt-on-pin change will cause an interrupt to occur if a pin changes to the opposite state. the default state is reset after an interrupt occurs and after clearing the interrupt condition (i.e., after reading gpio or intcap). for example, an interrupt occurs by an input changing from 1 to 0 . the new initial state for the pin is a logic 0 after the interrupt is cleared. 2. pins configured for interrupt-on-change from register value will cause an interrupt to occur if the corresponding input pin differs from the register bit. the interrupt condition will remain as long as the condition exists, regardless if the intcap or gpio is read. see figures 3-8 and 3-9 for more information on interrupt operations. figure 3-8: interrupt-on-pin change figure 3-9: interrupt-on-change from register default note: the value in intcap can be lost if gpio is read before intcap while another ioc is pending. after reading gpio, the interrupt will clear and then set due to the pending ioc, causing the intcap register to update. gpx int active active port value is captured into intcap read gpio or intcap port value is captured into intcap int port value is captured into intcap read gpio or intcap defval register x x x x x 0 x x gp2 76543210 gpx<7:0> active active (int clears only if interrupt condition does not exist.) pin pin downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 26 ? 2005-2016 microchip technology inc. 4.0 packaging information 4.1 package marking information mcp23017-e/so 3 e legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead soic example: 28-lead ssop yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx example: 28-lead qfn example: 28-lead spdip example: xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnn mcp23017-e/sp 1628256 3 e mcp23017 e/ss 3 e 1628256 23017 e/ml 1628256 3 e 1628256 downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 27 mcp23017/mcp23s17 downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 28 ? 2005-2016 microchip technology inc. downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 29 mcp23017/mcp23s17 !" # $ %&'' () ) $ * ! " # $ %!& !! ' # ( $ )**%%% * # downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 30 ? 2005-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 31 mcp23017/mcp23s17 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 32 ? 2005-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 33 mcp23017/mcp23s17 +)) , -)) + .%% !+ ,- " * ' ,!" $-( " , &." "! . $% $ /( 0 ! 1 ! ! $2 $ "$ $( ! "! ! $( ! "! !! -$ 3 !$ ! $ 24 + 50) 5 ! ! - , "! %% " ! * ! " # $ %!& !! ' # ( $ )**%%% * # 6 ! 7082 ! 9 ! 7 7: ; 7" . ('! 7 < ' 50 ' = = $$' # #!! 1+ + 5 ! ' + = = "$ "$ >$ 2 1 11+ $$' # >$ 2 <+ + :, 9 1+ 1?+ ' 9 1 + 9 $ #!! < + 6 9 $>$ . + 9 % 9 $>$ . < :, % / 5 = = 1 note 1 n 12 d e1 eb c e l a2 e b b1 a1 a 3 % 05 downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 34 ? 2005-2016 microchip technology inc. +$/) + 0 ) ++ '&.% !++0 " * ' ,!" $-( " , &." "! . $% $ ! ! $2 $ "$ $( ! "! ! $( ! "! !! -$ !$ 1 ! $ 24 + 50) 5 ! ! - , "! %% " ! 2 ) ( ! &"!" % " &( ( " !! * ! " # $ %!& !! ' # ( $ )**%%% * # 6 ! 992 2 ! 9 ! 7 7: ; 7" . ('! 7 < ' ?+50 :, 8 = = $$' # #!! ?+ + <+ $ (( + = = :, >$ 2 < < $$' # >$ 2 + +1 +? :, 9 + 9 9 ++ + + 9 +2 9 $ #!! = + @ @ <@ 9 $>$ . = 1< l l1 c a2 a1 a e e1 d n 1 2 note 1 b e % 015 downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 35 mcp23017/mcp23s17 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 36 ? 2005-2016 microchip technology inc. notes: downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 37 mcp23017/mcp23s17 appendix a: revision history revision c (july 2016) the following is the list of modifications: 1. added esd data to section 1.0, electrical characteristics . 2. updated ta b l e 2 - 1 . 3. updated package outline drawings. 4. minor typographical errors revision b (february 2007) 1. changed byte and sequential read in figure 1-1 from r to w. 2. table 2-4, param no. 51 and 53: changed from 450 to 600 and 500 to 600, respecively. 3. added disclaimers to package outline drawings. 4. updated package outline drawings. revision a (june 2005) original release of this document. downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 38 ? 2005-2016 microchip technology inc. notes: downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 39 mcp23017/mcp23s17 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp23017: 16-bit i/o expander with i 2 c interface mcp23s17: 16-bit i/o expander with spi interface temperature range: e=- 4 0 ? c to +125 ? c (extended) package: ml = plastic quad flat, no lead package, 6x6 mm body, qfn, 28-lead so = plastic small outline, wide, 7.50 mm body, soic, 28-lead sp = skinny plastic dual in-line, 300 mil body, spdip, 28-lead ss = plastic shrink small outline, 5.30 mm body, ssop, 28-lead tape and reel option: t = tape and reel ( 1 ) blank = tube part no. x /xx package temperature range device examples: a) mcp23017-e/ml: extended temperature, 28ld qfn package b) mcp23017t-e/ml: extended temperature, 28ld qfn package, tape and reel c) mcp23017-e/sp: extended temperature , 28ld spdip package d) mcp23017-e/so: extended temperature, 28ld soic package e) mcp23017t-e/so: extended temperature, 28ld soic package, tape and reel f) mcp23017-e/ss: extended temperature, 28ld ssop package g) mcp23017t-e/ss: extended temperature, 28ld ssop package, tape and reel a) mcp23s17-e/ml: extended temperature, 28ld qfn package b) mcp23s17t-e/ml: extended temperature, 28ld qfn package, tape and reel c) mcp23s17-e/sp: extended temperature, 28ld spdip package d) mcp23s17-e/so: extended temperature, 28ld soic package e) mcp23s17t-e/so: extended temperature, 28ld soic package, tape and reel f) mcp23s17-e/ss: extended temperature, 28ld ssop package g) mcp23s17t-e/ss: extended temperature, 28ld ssop package tape and reel C x ( 1 ) tape and reel option note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. downloaded from: http:/// mcp23017/mcp23s17 ds20001952c-page 40 ? 2005-2016 microchip technology inc. notes: downloaded from: http:/// ? 2005-2016 microchip technology inc. ds20001952c-page 41 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2005-2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0755-3 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:/// ds20001952c-page 42 ? 2005-2016 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-695-1980 fax: 905-695-2078 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - dongguan tel: 86-769-8702-9880 china - guangzhou tel: 86-20-8755-8029 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - karlsruhe tel: 49-721-625370 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 worldwide sales and service 06/23/16 downloaded from: http:/// |
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